The present invention relates to a selector circuit and a semiconductor device, and more particularly, to a selector circuit for selecting a given signal from a plurality of signals, and to a semiconductor device on which the selector circuit is mounted.
In recent years, semiconductor devices (LSIs) have been highly integrated and become multifunctional, and signals used therein have also been diversified. A selector circuit, which selects a given signal from a plurality of input signals and outputs the selected signal, is mounted on such an LSI. A subsequent circuit connected to the selector circuit operates according to an output signal of the selector circuit. Thus, the selector circuit is required to correctly propagate the waveform of its selected input signal to the subsequent circuit.
Conventional selector circuits have, for example, the structures shown in FIGS. 3 to 5.
FIG. 3 is a circuit diagram showing a selector circuit according to a first conventional example. The selector circuit 51 is, for example, a two-input selector circuit that uses two transfer gates (also referred to as transmission gates). The selector circuit 51 selects one of first and second data input signals IN1 and IN2 based on an externally input selection signal S, and outputs the selected signal. Each transfer gate is formed by connecting, for example, a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor in parallel.
In detail, in the selector circuit 51, the first data input signal IN1 is input into an input terminal of the first transfer gate 53 via an inverter circuit 52, and the second data input signal IN2 is input into an input terminal of the second transfer gate 55 via an inverter circuit 54. An output terminal of each of the transfer gates 53 and 55 is connected to an inverter circuit 56.
The first and second transfer gates 53 and 55 described above are controlled on and off complementarily, based on the externally input selection signal S. To be specific, the selection signal S is used to generate an internal selection control signal sn via an inverter circuit 57. The signal sn is input into the gate of the NMOS transistor included in the first transfer gate 53, and the gate of the PMOS transistor included in the second transfer gate 55. Also, the selection signal S is used to generate an internal selection control signal sp via the inverter circuit 57 and an inverter circuit 58. The signal sp is input into the gate of the PMOS transistor included in the first transfer gate 53, and the gate of the NMOS transistor included in the second transfer gate 55.
When the selection signal S is input at a low (L) level, the first transfer gate 53 is turned on and the second transfer gate 55 is turned off, so that the selector circuit 51 outputs the first data input signal IN1 as its output signal OUT. When the selection signal S at a high (H) level is input, the first transfer gate 53 is turned off and the second transfer gate 55 is turned on, so that the selector circuit 51 outputs the second data input signal IN2 as its output signal OUT.
FIG. 4 is a circuit diagram showing a selector circuit according to a second conventional example. The selector circuit 61 is, for example, a two-input selector circuit that uses a complex gate. In the same manner as described above, the selector circuit 61 selects one of first and second data input signals IN1 and IN2 based on an externally input selection signal S, and outputs the selected signal.
The complex gate is formed by first and second AND circuits 62 and 63 and a NOR circuit 64 (more precisely, a two-input NOR circuit having an AND function). An output terminal of the NOR circuit 64 is connected to an inverter circuit 65. The first data input signal IN1 is input into one input terminal of the first AND circuit 62. The selection signal S is input, as an internal selection control signal sn, into the other input terminal of the first AND circuit 62 via an inverter circuit 66. The second data input signal IN2 is input into one input terminal of the second AND circuit 63. The selection signal S (signal substantially the same as the internal selection control signal sp) is input into the other input terminal of the second AND circuit 63. In the same manner as described above, the selector circuit 61 outputs the first data input signal IN1 when the selection signal S is input at an L level, and outputs the second data input signal IN2 when the selection signal S at an H level is input.
FIG. 5 is a circuit diagram showing a selector circuit according to a third conventional example. The selector circuit 71 is shown as a selector circuit formed by using another complex gate. The complex gate is formed by first and second OR circuits 72 and 73 and a NAND circuit 74 (more precisely, a two-input NAND circuit having an OR function). An output terminal of the NAND circuit 74 is connected to an inverter circuit 75. A selection signal S (signal substantially the same as the internal selection control signal sp) is input into the first OR circuit 72. The selection signal S is input, as an internal selection control signal sn, into the second OR circuit 73 via an inverter circuit 76. In the same manner as described above, the selector circuit 71 with this structure also outputs a first data input signal IN1 when the selection signal S at an L level is input, and outputs a second data input signal IN2 when the selection signal S at an H level is input.
In the selector circuits 51, 61, and 71 according to the first to third conventional examples described above, the first and second data input signals IN1 and IN2, which are input therein, are signals asynchronous to each other having different frequencies. Thus, as shown in FIG. 6, a spike pulse waveform (hazard), a waveform with a short pulse width, etc. may appear in the output signal OUT, depending on the timing at which the selection signal S transits (transits to an H level or to an L level).
Such a defective pulse waveform (e.g. hazard) causes a subsequent circuit, which operates upon receipt of the signal, to malfunction. In particular, when the selector circuit is used for selecting clock signals, appearance of such a defective pulse waveform (e.g. hazard) has an influence on the operation of the subsequent logical circuit. Here, although FIG. 6 shows the case in which the first data input signal IN1 has a higher frequency than that of the second data input signal IN2, the same problem occurs also when the second data input signal IN2 has a higher frequency than that of the first data input signal IN1.
To solve this problem, the structures disclosed, for example, in Japanese Laid-Open Patent Publication Nos. 4-316113 and 5-291895, and the structure shown in FIG. 7 are conventionally proposed.
FIG. 7 is a circuit diagram showing a selector circuit according to a fourth conventional example. The selector circuit 81 includes a selector circuit unit 82, an EOR circuit 83, and a latch circuit unit 84.
In the same manner as described for the first conventional example (refer to FIG. 3), the selector circuit unit 82 is formed by using transfer gates. The selector circuit unit 82 selects one of first and second data input signals IN1 and IN2 based on a selection control signal sel, which is output from the latch circuit unit 84. The EOR circuit 83 determines whether the levels (transiting states) of the first and second data input signals IN1 and IN2 match. The EOR circuit 83 outputs an L level determination signal eq when the signal levels match, and outputs an H level determination signal eq when the signal levels do not match.
According to the determination signal eq, the latch circuit unit 84 propagates an externally input selection signal S and generates a selection control signal sel, or interrupts the input selection signal S and generates a selection control signal sel maintained at its output level. In detail, the latch circuit unit 84 generates internal control signals gn and gp based on the determination signal eq from the EOR circuit 83, and controls its two transfer gates 91 and 92 on and off complementarily, based on the signals gn and gp.
The latch circuit unit 84 propagates the externally input selection signal S and outputs the selection control signal sel in response to the determination signal eq at an L level (indicating that the levels of the signals IN1 and IN2 match). The latch circuit unit 84 interrupts the externally input selection signal S and maintains the selection control signal sel at its output level in response to the determination signal eq at an H level (indicating that the levels of the signals IN1 and IN2 do not match).
In other words, the latch circuit unit 84 propagates the transition of the selection signal S using the selection control signal sel only when the first and second data input signals IN1 and IN2 are both at an H level or both at an L level, i.e., only when the levels of the signals match. The selector circuit unit 82 performs a selection operation in response to the signal sel. This prevents a hazard or a waveform with an insufficient pulse width described above from appearing in the output signal OUT of the selector circuit unit 82.